The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed. For example, as geometry sizes shrink, conventional patterning processes (such as conventional photolithography processes) have difficulty forming IC features having small geometry sizes, particularly as technology nodes continue evolving to 20 nm and below. As a result, double patterning, extreme ultraviolet (EUV), and electron beam writing methods have been implemented to achieve these smaller geometry sizes. However, such methods introduce significant increase in manufacturing costs, and in some cases, significant increase in manufacturing processes (and thus manufacturing time). Accordingly, although existing IC patterning methods approaches have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.